Journal of Undergraduate Research
Volume 4, Issue 9 - June 2003

Investigation on a Dynamic Threshold Voltage Control via Body Bulk-Biasing as a Forth Terminal on a CMOS Process Technology

Joseph Robenson

ABSTRACT

As time reaches a threshold of tomorrow’s challenges in electron devices, namely, issues concerning power consumption due to leakage current, better control over transistor’s on and off states, and quantum effects; these issues underlie one principle phenomenon, a relentless pursuits in downsizing the transistor. A decade from today, The International Technology Roadmap for Semiconductor projects a minimum feature size of 50nm; that is one fifth of smallest size today. As feature size of a transistor shrinks beyond the 50nm, scientists and engineers must ensure that the transistor will effectively operate. The focus of my investigation is the issue of power consumption in electronic devices. While reducing the power supply and dynamically changing the threshold voltage by tying the substrate of Si based CMOS device to a potential source will increase the current drive of the device and actively reduce the low-static leakage power during idle periods of a system which will significantly reduce the total power consumption due to static leakage power dissipation.

INTRODUCTION

Gordon Moore, a chief executive officer of Intel Co., once predicted that the number of transistors in a single IC (Integrated Circuit) will exponentially increase as a function of time. Although this does not establish rules or a governing principle, today, we refer this as “Moore’s law” [1]. While Moore’s law have been a guiding frontier for semiconductor devices, as technological continuum reaches a threshold of tomorrow’s challenges, engineers and scientists journey into new sets of problems and solutions. Electronic devices are a driving factor in the areas of computation, instrumentation, telecommunication, and consumer electronics; however, designers and process engineers are struggling and confronting issues meeting new demands [2]. Since the time of Jack Kilby and Robert Noyce, technology has peaked due to its own physical limitations. National Technology Roadmap for Semiconductors (NTRS), by year 2012, projects a minimum feature size or the length of the channel in a transistor between the source and drain to be 50nm [3]. Consumers demand an increase in performance, a decrease in power consumption, and a cost efficient system. Thus, the drive for more transistors in smaller packages leads to numerous electro-physical complexities [4]. An alternative approach to consider is to divert our attention to a deliverable solution without completely replacing the current hierarchy of CMOS (Complimentary Metal to Oxide Semiconductor) technology. One of the current issues to consider is power consumption. Due to the present drive for portable electronic hand held devices, and to accommodate the consumer demands of highly efficient system, the electronic industries are now facing and confronting the issue of power consumption [2]. One of the solution is to bias the body or the bulk of the transistor as a fourth terminal which will effectively alter the value of the threshold voltage. This will produce a significant result in reducing static power consumption due to leakage current [2].

CURRENT APPROACHES

Samples Majority of the research in dynamic threshold is being conducted outside the U.S. with an exception of MIT and University of California Berkeley led by Professor Dimitri Antoniadis and Professor Jeffery Bokor. From total of nine distinguished papers published in the journals of IEEE from 1990s to the present day, two are from U.S., three are from China and Taiwan and four are from Japan.

The concept of dynamic threshold is a novel idea that connects “Gate-to-body by using aluminum to short the poly gate to the P+ region [6]” in a MOSFET (metal to oxide semiconductor field effect transistor) device invented by Dr. Fariborz Assaderaghi, Dr. Dennis Sinitsky, Dr. Stephen A. Parke, Dr. Jeffery Bokor, Dr. Ping K. Ko, and Dr. Chenming Hu. This device, known as DTMOS, is not the dawn of a new technology. Rather, this technology is at the brink of an optimization phase where application and implementation is the key.

DISCUSSION AND ANALYSIS

NF1 On May 1997, IEEE transaction on Electron Device explored key methods and theories contributing to the issue of static power consumption in electronic devices. Professor Dimitri Antoniadis and the MIT Semiconductor Devices and Microelectronics Group in conjunction with IBM, published a paper in the journal of IEEE addressing a novel implementation of back-gate CMOS on SOIAS (Silicon On Insulator on Active Substrate) for dynamic threshold control in attempt to reduce the static power consumption.

The Back-gated CMOS on SOIAS simultaneously reduces the power supply and the threshold voltage without suffering losses to performance. Furthermore, it reduces static leakage power dissipation [5]. This is a significant portion of total power consumption on electronic devices especially during idle periods. To implement this idea, Professor Antoniadis proposed a novel approach using a SOI based technology called Silicon on Insulator with Active Substrate. To demonstrate this, the he used a selectively sealed CMOS process implementing discrete devices and a ring oscillator which produced a result of a 250mv switch in Vt and a reduction of 3-4 decades in sub-threshold leakage current [5].

SOIAS Concept

The concept of SOIAS is fundamentally adding one or more conductive under layers beneath the buried oxide of a SOI structure. Such layer can be served as a buried interconnect, gate or both. The fabrication of SOIAS structure leverages off from bulk and SOI CMOS processes [5].

Figure 1. SOIAS Process

Figure 1. SOIAS Process


Dynamic Treshold Voltage Control Concept

There are two types of systems, systems that operate in a burst mode or systems that operate in a continuous mode. “A global strategy for achieving high performance and low power consumption in continuously computing systems has been simultaneous reducing the supply voltage Vdd and threshold voltage Vt” [5]. For CMOS-based high performance burst-mode computation system, it will suffer high static power dissipation at low Vdd with constant Vt even during idle periods [5]. An example of such system is a cell phone, which is at idle periods more than 90% of the time. In order to achieve high performance during active periods and low leakage power during idle periods for burst mode computational system, several schemes of reducing the leakage current have been proposed [5]:

    • multiple Vt CMOS design
    • dynamic control of Vt by biasing the bulk CMOS wells

This approach requires a triple well technology. However, well biasing becomes more complicated due to junction leakage currents.

DTMOS Concept

To introduce Dynamic threshold MOSFET, let’s first review the concept of Body bias effect. When applying a voltage to the Si substrate, the device can be modeled as following: [7]

Figure 2. Body Bias Effect

Figure 2. Body Bias Effect

Notice that the threshold voltage changes as a function of doping concentration and Vbs. DTMOS operates by biasing the gate and body together. By reducing the threshold voltage, the electron mobility will increase, therefore, performance will increase. Furthermore, by increasing the threshold voltage during idle periods will decrease the leakage current. To demonstrate this, DTMOS use the following design topology: [6]

Figure 3. DTMOS Design Topology

Figure 3. DTMOS Design Topology

To implement this in design layout tool, see the figures below: [6]

Figure 4. Design Layout
Figure 4. Design Layout
Figure 5. Gate to Body contact Cross Section
Figure 5. Gate to Body contact Cross Section

Body bias effect is normally studied in the reversed bias regime; however, DTMOS operates in the exact opposite regime. Body-source junction is forward biased at less then 0.6 v, forcing the Vt to drop during the operating periods [6]. Thus, lower Vt leads to a higher mobility. Higher mobility and larger inversion charge lead to a higher current drive in DTMOS [6].

Figure 6. DTMOS vs. Standard MOS
Figure 6. DTMOS vs. Standard MOS

Because the current drive of DTMOS is much higher than that of the standard MOSFET, DTMOS gates will switch faster than the standard MOSFET.

CONCLUSION

While pursuing this investigation on a dynamic threshold voltage control via body bulk-biasing as a forth terminal on a CMOS process technology, there are several unmet challenges: issues concerning power consumption due to leakage current, better control over transistor’s on and off states, and quantum effects. These issues underlie one principle phenomenon, a relentless pursuits in downsizing the transistor for optimization. As minimum feature size of a transistor shrinks beyond the 50nm, scientists and engineers must ensure the operation of transistors. This requires further investigation in the following areas:

• Improvement in Performance → Si mixed with Germanium to produce a more spacious, strained crystalline structure that let electrical charge carrier move faster (Strained Silicon)

• Reduction in leakage current → gate oxide made of materials with more than 8 times the dielectric constant of SiO2 (Hafnium Dioxide)

• Optimum Control over transistor on and off state → gate made from metal instead of poly-silicon

• Reduction in power consumption → double gate implementation

Among these areas, only strained Si is being commercialized currently, and the rest are still in research and development stage [8]. Next to develop is the combination of higher dielectric constant and mental gate. AmberWave System Corp. developed a version of strained Si in collaboration with Bell lab and MIT [8]. In 2001, AmberWave began licensing to wafer and IC manufacturers thus, commercialization will soon emerge as companies develop their ideas into manufacturing process.

Unlike other techniques, double gate implementation, while still under research and development, projects to be the key design in efforts to reduce power consumption in portable electronic devices. Fully Depleted device is the principle governing this phenomenon. Currently, double gate implementation is being modeled in computer simulation led by Professor Fossum and the SOI group at University of Florida and fabricated at MIT Lincoln Lab.

REFERENCES

  1. Gordon Moore was one the founders of Intel and predicted this “law” around 1970.

  2. Stephan Ohr and Anthony Cataldo, “Designers confront costs of SoC scaling, integration,” EE Times, Conferences, http://www.eet.com/conf/OEG20011109S0096 [Nov. 2001]

  3. “National Technology Roadmap for Semiconductors.” SIA, 1997.

  4. Plummer, James D. D., Griffin, Peter B., Deal, Michael D., Griffin, Peter B. and Michael D. Deal, Silicon VLSI Technology: Fundamentals, Practice, and Modeling. Prentice Hall Professional Technical Reference, July 2000, pp 4.

  5. Isabel Y. Yang, Carlin Vieri, Anantha Chandrakasan, and Dimitri A. Antoniadis, “Back-gated CMOS on SOIAS for dynamic threshold voltage control,” IEEE Trans. Electron Devices, Vol. 44, No. 5, pp. 822-830, May 1997.

  6. Fariborz Assaderaghi, Dennis Sinitsky, Stephen A. Parke, Jeffery Bokor, Ping K. Ko, and Chenming Hu, “Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI,” IEEE Trans. Electron Devices, Vol. 44, NO. 3, pp. 414-422, March 1997.

  7. Taur, Yuan and Tak H. Ning. Fundamentals of Modern VLSI Devices. Cambridge University Press 1998, pp129-130.

  8. Geppert, Linda. “Amazing Vanishing Trasistor Act.” IEEE Spectrum. October 2002. pp28-34.

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